In the prior art, arithmetic logic units (ALUs) typically operate with binary word sizes of a given bit length; such as eight, sixteen or thirty-two bits. Adjunct to the ALUs are circuits that store indicator information such as overflow, carry, arithmetic sign and all bits equal zero that are generated by the ALU while processing binary information words. An arithmetic sign result of a computation is usually stored in and taken from a particular bit location in the binary words, and a carry from the computation involving addition of two binary numbers is taken from the highest order bit position of the binary numbers being processed.
However, there is a problem in the prior art when shorter bit length binary words are to be processed in a system designed for operation with a longer bit length binary word. For example, a carry indicator bit must be detected from a lower order bit location than when the ALU is operating with binary words of full bit length.
Thus, there is a need in the art for a multifunction arithmetic indicator that can function with an ALU that is designed to handle binary words having more than one bit length. Such an indicator should be able to receive and temporarily store standard arithmetic indicator information such as overflow, carry, arithmetic sign and all zeroes condition of computation result despite variable bit length binary words being processed by the ALU.